Ycarus Gentoo ebuild

vowstar

These ebuilds come from .

If you have some problems, go to the official site first.

sci-electronics

bluespec : Toolchain for the Bluespec Hardware Definition Language ( https://github.com/B-Lang-org/bsc )

chisel-meta : Meta package to run chisel playground ( https://github.com/chipsalliance/playground )

circt : The fast free Verilog/SystemVerilog simulator ( HOMEPAGE=" )

coil64 : Coil64 is inductance coil calculator ( HOMEPAGE=" )

digilent-adept-runtime : The Adept Runtime to communicate with Digilent's devices ( https://digilent.com/shop/software/digilent-adept )

digilent-adept-utilities : The Adept Utilities to communicate with Digilent's devices ( https://digilent.com/shop/software/digilent-adept )

dsview : An open source multi-function instrument ( HOMEPAGE=" )

iverilog : A Verilog simulation and synthesis tool ( HOMEPAGE=" )

jlc-assistant-bin : JLC Order Assistant (binary package) ( https://www.jlc.com/portal/appDownloadsWithConfig.html )

kactus2 : A open source IP-XACT-based tool ( HOMEPAGE=" )

kicad : Electronic Schematic and PCB design tools ( https://www.kicad.org )

kicad-footprints : Electronic Schematic and PCB design tools footprint libraries ( https://gitlab.com/kicad/libraries/kicad-footprints )

kicad-meta : Electronic Schematic and PCB design tools (meta package) ( http://www.kicad.org )

kicad-packages3d : Electronic Schematic and PCB design tools 3D package libraries ( https://gitlab.com/kicad/libraries/kicad-packages3D )

kicad-symbols : Electronic Schematic and PCB design tools symbol libraries ( https://gitlab.com/kicad/libraries/kicad-symbols )

kicad-templates : Electronic Schematic and PCB design tools project templates ( https://github.com/kicad/kicad-templates )

pulseview : Qt based logic analyzer GUI for sigrok ( https://sigrok.org/wiki/PulseView )

slang : SystemVerilog compiler and language services ( HOMEPAGE=" )

systemc : A C++ based modeling platform for VLSI and system-level co-design ( HOMEPAGE=" )

verible : SystemVerilog parser, style-linter, and formatter ( HOMEPAGE=" )

verilator : The fast free Verilog/SystemVerilog simulator ( HOMEPAGE=" )

wavedrom-cli : WaveDrom command-line interface ( HOMEPAGE=" )

wavedrom-editor-bin : Digital timing diagram editor ( HOMEPAGE=" )

yosys : framework for Verilog RTL synthesis ( http://www.clifford.at/yosys/ )

Add an ebuild in portage :

The ebuild is now in the portage tree.

You can also use layman : emerge layman then layman -a vowstar

For Paludis use this rsync : rsync://gentoo.zugaina.org/vowstar-portage

If you have a problem : ycarus(-at-)zugaina.org