bluespec : Toolchain for the Bluespec Hardware Definition Language ( https://github.com/B-Lang-org/bsc )
chisel-meta : Meta package to run chisel playground ( https://github.com/chipsalliance/playground )
circt : The fast free Verilog/SystemVerilog simulator ( HOMEPAGE=" )
iverilog : A Verilog simulation and synthesis tool ( HOMEPAGE=" )
kicad : Electronic Schematic and PCB design tools ( https://www.kicad.org )
kicad-footprints : Electronic Schematic and PCB design tools footprint libraries ( https://gitlab.com/kicad/libraries/kicad-footprints )
kicad-i18n : Electronic Schematic and PCB design tools GUI translations ( https://gitlab.com/kicad/code/kicad-i18n )
kicad-packages3d : Electronic Schematic and PCB design tools 3D package libraries ( https://gitlab.com/kicad/libraries/kicad-packages3D )
kicad-symbols : Electronic Schematic and PCB design tools symbol libraries ( https://gitlab.com/kicad/libraries/kicad-symbols )
kicad-templates : Electronic Schematic and PCB design tools project templates ( https://github.com/kicad/kicad-templates )
klayout : Viewer and editor for GDS and OASIS integrated circuit layouts ( https://www.klayout.de/ )
slang : SystemVerilog compiler and language services ( HOMEPAGE=" )
systemc : A C++ based modeling platform for VLSI and system-level co-design ( HOMEPAGE=" )
verible : SystemVerilog parser, style-linter, and formatter ( HOMEPAGE=" )
verilator : The fast free Verilog/SystemVerilog simulator ( HOMEPAGE=" )
Pour rajouter une e-build dans l'arbre de portage :
L'ebuild est alors rajouté dans l'arbre de portage.
Vous pouvez aussi utiliser layman : emerge layman puis layman -a vowstar
Pour Paludis utilisez ce rsync : rsync://gentoo.zugaina.org/vowstar-portage
En cas de problèmes : ycarus(-at-)zugaina.org