bender : A dependency management tool for hardware projects ( https://github.com/pulp-platform/bender )
bluespec : Toolchain for the Bluespec Hardware Definition Language ( https://github.com/B-Lang-org/bsc )
chisel-meta : Meta package to run chisel playground ( https://github.com/chipsalliance/playground )
circt : The fast free Verilog/SystemVerilog simulator ( HOMEPAGE=" )
cocotb : Python-based chip (RTL) verification ( https://www.cocotb.org )
cocotb-bus : Reusable testbenching tools and bus interfaces for cocotb ( https://github.com/cocotb/cocotb-bus )
coil64 : Coil64 is inductance coil calculator ( HOMEPAGE=" )
digilent-adept-runtime : The Adept Runtime to communicate with Digilent's devices ( https://digilent.com/shop/software/digilent-adept )
digilent-adept-utilities : The Adept Utilities to communicate with Digilent's devices ( https://digilent.com/shop/software/digilent-adept )
dsview : An open source multi-function instrument ( HOMEPAGE=" )
iverilog : A Verilog simulation and synthesis tool ( HOMEPAGE=" )
jlc-assistant-bin : JLC Order Assistant (binary package) ( https://www.jlc.com/portal/appDownloadsWithConfig.html )
kactus2 : A open source IP-XACT-based tool ( HOMEPAGE=" )
kicad : Electronic Schematic and PCB design tools ( https://www.kicad.org )
kicad-footprints : Electronic Schematic and PCB design tools footprint libraries ( https://gitlab.com/kicad/libraries/kicad-footprints )
kicad-meta : Electronic Schematic and PCB design tools (meta package) ( http://www.kicad.org )
kicad-packages3d : Electronic Schematic and PCB design tools 3D package libraries ( https://gitlab.com/kicad/libraries/kicad-packages3D )
kicad-symbols : Electronic Schematic and PCB design tools symbol libraries ( https://gitlab.com/kicad/libraries/kicad-symbols )
kicad-templates : Electronic Schematic and PCB design tools project templates ( https://github.com/kicad/kicad-templates )
systemc : A C++ based modeling platform for VLSI and system-level co-design ( HOMEPAGE=" )
vcd : VCD file (Value Change Dump) command line viewer ( https://github.com/yne/vcd )
verible : SystemVerilog parser, style-linter, and formatter ( HOMEPAGE=" )
verilator : The fast free Verilog/SystemVerilog simulator ( HOMEPAGE=" )
wavedrom-cli : WaveDrom command-line interface ( HOMEPAGE=" )
wavedrom-editor-bin : Digital timing diagram editor ( HOMEPAGE=" )
yosys : framework for Verilog RTL synthesis ( http://www.clifford.at/yosys/ )
Pour rajouter une e-build dans l'arbre de portage :
L'ebuild est alors rajouté dans l'arbre de portage.
Vous pouvez aussi utiliser layman : emerge layman puis layman -a vowstar
Pour Paludis utilisez ce rsync : rsync://gentoo.zugaina.org/vowstar-portage
En cas de problèmes : ycarus(-at-)zugaina.org
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