bender : A dependency management tool for hardware projects ( https://github.com/pulp-platform/bender )
bluespec : Toolchain for the Bluespec Hardware Definition Language ( https://github.com/B-Lang-org/bsc )
circt : The fast free Verilog/SystemVerilog simulator ( HOMEPAGE=" )
cocotb : Python-based chip (RTL) verification ( https://www.cocotb.org )
cocotb-bus : Reusable testbenching tools and bus interfaces for cocotb ( https://github.com/cocotb/cocotb-bus )
coil64 : Coil64 is inductance coil calculator ( HOMEPAGE=" )
dsview : An open source multi-function instrument ( HOMEPAGE=" )
liblxi : Implementation of the LAN eXtensions for Instrumentation (LXI) ( https://github.com/lxi-tools/liblxi )
logic-bin : Saleae logic analyzer ( https://www.saleae.com )
lxi-tools : Tools to access devices with LXI ( https://github.com/lxi-tools/lxi-tools )
qucs-s : Quite universal circuit simulator with SPICE ( https://ra3xdh.github.io/ )
svls : SystemVerilog language server ( https://github.com/dalance/svls )
vcd : VCD file (Value Change Dump) command line viewer ( https://github.com/yne/vcd )
verilator : The fast free Verilog/SystemVerilog simulator ( HOMEPAGE=" )
yosys : framework for Verilog RTL synthesis ( http://www.clifford.at/yosys/ )
Pour rajouter une e-build dans l'arbre de portage :
L'ebuild est alors rajouté dans l'arbre de portage.
Vous pouvez aussi utiliser layman : emerge layman puis layman -a guru
Pour Paludis utilisez ce rsync : rsync://gentoo.zugaina.org/guru-portage
En cas de problèmes : ycarus(-at-)zugaina.org
